1. Field of the Invention
The present invention relates generally to electronic circuits, and more specifically to functional modules on a single semiconductor integrated circuit.
2. Description of the Prior Art
The semiconductor art has advanced to the point where whole systems are preferably integrated onto a single-chip device. Processing speeds and architectures are such that very wide buses operated at near gigaHertz speeds are routinely used to interface processors, peripherals, and memory. Single-chip system-on-chip (SOC) implementations now permit several such buses to be switched between resources. Off chip, such a bus switch architecture would be impractical.
Palmchip Corporation (San Jose, Calif.) markets its COREFRAME(trademark) products to be low-power, high-performance, processor independent, flexible on-chip interconnect architectures for integration of system-on-chip (SOC) blocks in a synthesis-friendly environment. COREFRAME designs combine different processors, systems with resource routers and dynamic bandwidth allocation, systems with multiple clock domains, and systems with a non-memory shared resource and without a processor. COREFRAME can interface between multiple bus standards, as well as fast and slow non-DMA devices on a single channel.
Von Neumann and Harvard are two of the most common computer types in use today. A Von Neumann architecture processor uses the same external buses for instruction fetches and data operations in a shared arrangement. A Harvard architecture processor uses separate buses for instruction fetches and data operations. Most digital signal processor (DSP) designs today use the Harvard architecture because the performance benefits far outweigh the cost of adding extra wires and pins.
A simple bus architecture is basically a modified external bus standard using unidirectional buses for on-chip data transfers, e.g., separate read data and write data busses. There are several variations of this basic theme, for example, the peripherals may be bridged directly off the CPU or the peripheral bus may be removed entirely and the slower peripheral targets may be mixed with the fast targets on the high-speed bus. There are many variations in bus protocol, and arbitration, that try to optimize the throughput, all data passes over the same wires and there is no parallelism. The bandwidth is simply determined by the width of the data path and the clock frequency. In order to increase bandwidth, the width of the data path and/or clock frequency must be increased. But these increases only work up to the point where most transfers in a typical system are not a full data path wide.
When placing and routing this architecture the high-speed bus must run to all the initiators and targets, which usually means that this bus must run all the way across the chip. In order to keep the high-speed bus running at high speed, special layout techniques must be used which will kill the time to market advantages of system-on-chip design.
A variation of the simple bus architecture uses multiple high speed buses with a bridges between them and thereby allows some parallelism. Transactions on bus-A can proceed at the same time bus-B is busy. But still has the same problem as above in that each initiator can still talk to each target across the bridge. This means the bus still routes across the chip and will have problems at high clock frequencies. In addition when an initiator on bus-A talks to a target on bus B both bus-A and bus-B are tied up. The bridge also adds two levels of logic to the data, address, and control signals making it the limiting factor for performance.
The point-to-point architecture can only be used to its fullest in on-chip designs due to package-pin limitations. In this architecture multiple initiators connect directly to each target through a switching network. Each initiator must arbitrate for the target, but once connected the transfers occur at full bandwidth. The number of target devices determines the maximum bandwidth. This architecture removes many of the disadvantages of the simple bus architecture in that the unnecessary connections are eliminated and portions of the switching network are routed locally. Transactions can operate in parallel. A disadvantage of the point-to-point architecture is the number of accessible target devices is limited. As more and more targets are added, the switching network becomes more difficult to implement. Changes to the switching network in the middle of the design become practically impossible.
It is therefore an object of the present invention to provide a system-on-chip interconnection structure and method for efficient integration of a variety of functional circuits.
It is a further object of the present invention to provide an on-chip interconnect architecture that standardizes how systems-on-chip are fabricated on silicon semiconductor integrated circuit chips.
Briefly, a system resource router embodiment of the present invention interfaces initiators through protocol adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.
An advantage of the present invention is that a system resource router is provided that divides a high-speed bus into M-channel sub busses and uses switches at initiator sockets to connect to the different M-channels.
Another advantage of the present invention is that while dividing a high bus into M-channel sub busses erroneous connections can be removed and each M-channel sub bus can be routed locally.
Another advantage of the present invention is that a system resource router is provided that allows different initiator-to-target or memory transactions to occur simultaneously across different M-channels.
A further advantage of the present invention is that a system resource router is provided that increases the bandwidth of the system without resorting to larger bus widths or higher clock frequencies.